CMV8000 datasheet(21/90 Pages) AMSOSRAM

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CMV8000

Functional Description

Preliminary Datasheet

• PUBLIC

DS000609

• v1-00 • 2019-Jun-12

│ 20

7.1.2

Analog Front End

The analog front-end (AFE) consists of two major parts: a column amplifier block and a column ADC

block.

The column amplifier prepares the pixel signal for the column ADC and applies an analog gain,

programmable through the serial interface.

The column ADC converts the analog pixel value to a 10-bit or 12-bit value. A digital offset can also be

applied to the output of the column ADCs.

7.1.3

DPP

The digital data block performs some operations on the digitized pixel data such as digital gain and

digital offset adjustment.

7.1.4

LVDS Block

The LVDS block and serializer convert digital pixel data into standard serial LVDS data running at a

maximum of 600 Mbps. The sensor has 18 LVDS output pairs.

●

16 data channels

●

1 control channel

●

1 clock channel

The 16 data channels are used to transfer 10-bit or 12-bit words of pixel data from sensor to receiver.

The output clock channel is a DDR clock, synchronous to the data on the other LVDS channels. This

clock should be used at the receiving end to sample the data. The control channel contains the sync

codes for the data channels (DVAL, LVAL, FVAL) and other useful information about the sensor

status, such as the integration pulse.

As LVDS is a differential interface, it requires impedance matched traces and a parallel termination at

the receiver side. On the sensor input clock IN_LCLK_P (pin T1) and IN_LCLK_N (pin U2), an

external 100

Ω resistor should be added. In the same manner, all the LVDS outputs should be

terminated at the FPGA side. See the TIA/EIA-644A standard for more details.

7.1.5

Sequencer

The on-chip sequencer will generate all required control signals to operate the sensor from only a few

external control clocks. This sequencer can be activated and programmed through the SPI interface.

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