RL78/G1M, G1N

2. ELECTRICAL SPECIFICATIONS

R01DS0378EJ0100 Rev.1.00

21 of 28

May 29, 2020

(2) CSI mode (master mode, SCKp...internal clock output)

(TA = –40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

SCKp cycle time

tKCY1

tKCY1

≥ 4/fCLK

2.7 V

≤ VDD ≤ 5.5 V

200

ns

2.0 V

≤ VDD ≤ 5.5 V

800

ns

SCKp high-/low-level width

tKH1, tKL1

2.7 V

≤ VDD ≤ 5.5 V

tKCY1/2 – 18

ns

2.0 V

≤ VDD ≤ 5.5 V

tKCY1/2 – 50

ns

SIp setup time (to SCKp

↑)Note 1

tSIK1

2.7 V

≤ VDD ≤ 5.5 V

47

ns

2.0 V

≤ VDD ≤ 5.5 V

110

ns

SIp hold time (from SCKp

↑)Note 1

tKSI1

19

ns

Delay time from SCKp

↓ to SOp

outputNote 2

tKSO1

C = 30 pFNote 3

25

ns

Notes 1. When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1. The SIp setup time becomes “to SCKp

↓” and

SIp hold time becomes “from SCKp

↓” when DAP0n = 0 and CKP0n = 1, or DAP0n = 1 and CKP0n = 0.

2. When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1. The delay time to SOp output becomes “from

SCKp

↑” when DAP0n = 0 and CKP0n = 1, or DAP0n = 1 and CKP0n = 0.

3. C is the load capacitance of the SCKp and SOp output lines.

Remark p: CSI number (p = 00), n: Channel number (n = 0)