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MK50H27DIP Datasheet(PDF) 42 Page - STMicroelectronics

Part # MK50H27DIP
Description  Signalling System 7 Link Controller
PDF  56 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

MK50H27DIP Datasheet(HTML) 42 Page - STMicroelectronics

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SECTION 5
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
TUB
Temperature Under Bias
-25 to +100
°C
Tstg
Storage Temperature
-65 to +150
°C
VG
Voltage on any pin with respect to ground
-0.5 to VCC+0.5
V
Ptot
Power Dissipation
0.5
W
Stresses above those listed under ”Absolute Maximum Rating” may cause permanent damage to the above device.
This is a stress rating only and functional operation of the device at these or any other condition above those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
DC CHARACTERISTICS
TA=0
°Cto70 °C, VCC =+5 V ±5 percent unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
Units
VIL
-0.5
+0.8
V
VIH
+2.0
VCC+0.5
V
VOL
@ IOL = 3.2 mA
+0.5
V
VOH
@ IOH= -0.4 mA
+2.4
V
IIL
@ VIN = 0.4 to VCC
+10
mA
ICC
@ TSCT = 100 ns
50
µA
CAPACITANCE
f = 1MHz
Symbol
Parameter
Min.
Typ.
Max.
Units
CIN
Capacitance on Input pins
10
pF
COUT
Capacitance on Output Pins
10
pF
CIO
Capacitance on I/O pins
20
pF
AC TIMING SPECIFICATIONS
TA =0
°Cto 70 °C, VCC =+5 V ±5 percent, unless otherwise specified.
MK50H27
-16
-25
-33
-16/25/33
No
Signal
Symbol
Parameter
Test Condition
Min.
Min.
Min.
Max.
Units
1
SYSCLK
TSCT
SYSCLK period
60
40
30
10000
ns
2
SYSCLK
TSCL
SYSCLK low time
24
16
12
ns
3
SYSCLK
TSCH
SYSCLK high time
24
16
12
ns
4
SYSCLK
TSCR
Rise time of SYSCLK
0
0
0
8
ns
5
SYSCLK
TSCF
Fall time of SYSCLK
0
0
0
8
ns
6
TCLK
TTCT
TCLK period
20
20
20
ns
7
TCLK
TTCL
TCLK low time
8
8
8
ns
8
TCLK
TTCH
TCLK high time
8
8
8
ns
9
TCLK
TTCR
Rise time of TCLK
CL = 50 pF
0
0
0
8
ns
10
TCLK
TTCF
Fall time of TCLK
0
0
0
8
ns
11
TD
TTDP
TD data propagation
delay after the falling
edge of TCLK
CL = 50 pF
13
ns
12
TD
TTDH
TD data hold time after
the falling edge of TCLK
555
ns
MK50H27
42/56



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