MK50H28DIP datasheet(12/64 Pages) STMICROELECTRONICS

12 / 64 page

INIT BLOCK

PTR TO INIT

MODE

PTR TO ALT

PTR TO STATUS

PTR TO CT

ADDRESS

LOOKUP

TABLE

RING0

XMIT

BUFF

BUFF ADDRESS

BUFF SIZE

BUFF MSG CNT

DESC 0

TIMER VALUES

ACT. CHNL

(1 ENTRY/ACT. CHNL)

BUFFERS

DATA

ACTIVE CHNL. 1

ACTIVE CHNL. N

TABLE

CONTEXT

RING N

XMIT

BUFF SIZE

BUFF MSG CNT

DESC 0

DESC 1

DESC M

BUFF

DESC 1

DESC N

BUFF ADDRESS

BUFF

LMI ERROR

STATUS

BUFFER

CSR2, CSR3

COUNTERS

BUFF

RX RING N

DESC 0

DESC 1

BUFF

DESC Y

BUFFERS

DATA

BUFF ADDRESS

BUFF SIZE

BUFF MSG CNT

BUFF

RX RING 0

DESC 0

DESC 1

BUFF

DESC X

BUFFERS

DATA

BUFF ADDRESS

BUFF SIZE

BUFF MSG CNT

BUFF

DESC RING PTRS

ACTIVE CHNL. 0

CONG STA TISTICS

DLCI / ADDRESS

CONG STATISTIC S

DLCI / ADDRESS

DESC RING PTRS

CONG STA TISTICS

DLCI / ADDRESS

DESC RING PTRS

BUFFER

(DLCI 0

DLCI 1024

PRIORITY DLCI

BLOCK

DLCI 8192)

RX INTERRUPT RING

DESC 0

DESC 1

DESC 127

RX CT Address

Current RX Desc

Service Bit

TX INTERRUP T RING

DESC 0

DESC 1

DESC 127

TX CT Address

Current TX Desc

Service Bit

PTR TO TINT DR

PTR TO RINT DR

Figure 3: MK50H28 Memory Management Structure

MK50H28

12/64

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