LXT9761 datasheet(13/78 Pages) INTEL

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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781

Datasheet

Table 1.

LXT97x1 RMII Signal Descriptions

9761 Pin#

9781 Pin#

Symbol

Type1

Signal Description2, 3

PQFP

PBGA

RMII Data Interface Pins

Y15

REFCLK

Reference Clock. 50 MHz RMII reference clock is required

at this pin. The LXT97x1 samples RMII inputs on the rising

edge of REFCLK, and drives RMII outputs on the falling

edge.

TXD0_0

TXD0_1

Transmit Data - Port 0. Inputs containing 2-bit parallel di-bits

to be transmitted from port 0 are clocked in synchronously to

REFCLK.

TXD1_0

TXD1_1

Transmit Data - Port 1. Inputs containing 2-bit parallel di-bits

to be transmitted from port 1 are clocked in synchronously to

REFCLK.

TXD2_0

TXD2_1

Transmit Data - Port 2. Inputs containing 2-bit parallel di-bits

to be transmitted from port 2 are clocked in synchronously to

REFCLK.

TXD3_0

TXD3_1

Transmit Data - Port 3. Inputs containing 2-bit parallel di-bits

to be transmitted from port 3 are clocked in synchronously to

REFCLK.

TXD4_0

TXD4_1

Transmit Data - Port 4. Inputs containing 2-bit parallel di-bits

to be transmitted from port 4 are clocked in synchronously to

REFCLK.

TXD5_0

TXD5_1

Transmit Data - Port 5. Inputs containing 2-bit parallel di-bits

to be transmitted from port 5 are clocked in synchronously to

REFCLK.

–

TXD6_0

TXD6_1

Transmit Data - Port 6. Inputs containing 2-bit parallel di-bits

to be transmitted from port 6 are clocked in synchronously to

REFCLK.

–

TXD7_0

TXD7_1

Transmit Data - Port 7. Inputs containing 2-bit parallel di-bits

to be transmitted from port 7 are clocked in synchronously to

REFCLK.

–

TXEN0

TXEN1

TXEN2

TXEN3

TXEN4

TXEN5

TXEN6

TXEN7

Transmit Enable - Ports 0 - 7. Active High input enables

respective port transmitter. This signal must be synchronous

to the REFCLK.

RXD0_0

RXD0_1

Receive Data - Port 0. Receive data signals (2-bit parallel di-

bits) are driven synchronously to REFCLK.

RXD1_0

RXD1_1

Receive Data - Port 1. Receive data signals (2-bit parallel di-

bits) are driven synchronously to REFCLK.

1. Type Column Coding: I = Input, O = Output, OD = Open Drain

2. The LXT97x1 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,

where X is the register number (0-32) and Y is the bit number (0-15).

3. Ports 6 and 7 are available only on the LXT9781. These pins are not bonded out on the LXT9761.

LXT9761 Datasheet(PDF) 13 Page - Intel Corporation

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