Application information

RHF1401

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Data ready (DR)

The data ready output signal is an image of the clock being synchronized on the output data

(D0 to D13). This is a very helpful signal that simplifies the synchronization of the

measurement equipment or the controlling DSP.

As all other digital outputs, DR goes into high impedance state when OEB reaches high

level as described in Figure 3: Timing diagram on page 7.

Caution:

Because the driving force of data outputs and the DR signal is relatively low, it is

recommended to limit the equivalent load on these signals to 10-15pF maximum. This is to

avoid a weak signal when the RHF1401 is clocked at full speed (20Msps). The DR signal is

potentially the most affected because it has the highest frequency (20MHz maximum).

If the equivalent load on the data outputs is slightly higher than 15pF, you can avoid

resorting to external re-buffering of the data bus and DR signal by connecting the data bus

to the acquisition device directly without using the DR. In this case, you can obtain a good

validation signal from a derivation of the clock because the clock falling edge is used by the

RHF1401 internally to generate data output transitions. A series resistor of approximately

100-200 Ohms should be placed at the derivation to avoid the effect of current spikes on the

critical CLK node. This configuration is illustrated in Figure 25.

Figure 25.

CLK signal derivation

CLK

50

Ω

100-200

Ω

D0-D13

DR

ASIC or FPGA

above 15pF