PC87108AVHG datasheet(13/56 Pages) NSC

13 / 56 page

2.0 Functional Description (Continued)

Since various operational modes are supported, the transmitter power as well as the receiver filter in the transceiver module must

be configured according to the selected mode.

The PC87108A provides four special interface pins (ID/IRSL[2–0] and ID3) to control the infrared transceiver. The logic levels of

the ID/IRSL[2–0] pins can be either directly controlled by the software (through the setting of bits 2–0 in the IRCFG1 register),

or can be automatically selected by the device whenever a new mode is entered.

The automatic transceiver configuration is enabled by setting the AMCFG bit in the IRCFG4 register to 1. One of its advantages

is that it allows the low-level functional details of the transceiver module being used to be hidden from the software drivers. It also

speeds up the transceiver mode selection, and it must be enabled if the pipelining feature is to be used.

The operational mode settings for the automatic configuration are determined by various bit fields in the IRCFGn registers that

must be programmed when the device is initialized.

The ID/IRSL[2–0] pins will power up as inputs and can be driven by an external source. When in input mode, they can be used

to read the identification data of Plug-n-Play infrared adapters. The ID3 pin is input-only and is also used for this purpose.

The ID0/IRSL0/IRRX2 pin can also function as an input to support an additional infrared receive signal. In this case, however, only

two configuration pins will be available. The IRSL0__DS and IRSL21__DS bits in the IRCFG4 register determine the direction of

the ID/IRSL[2–0] pins.

3.0 Architectural Description

Eight register banks are provided to control the operation of the UIR module. These banks are mapped into the same address

range, and only the selected bank is directly accessible by the software. The address range spans 8 byte locations. The BSR reg-

ister is used to select the bank and is common to all banks. Therefore, each bank defines seven new registers. The register banks

can be divided into two sets. Banks 0–3 are used to control both UART and infrared modes of operation; banks 4–7 are used to

control and configure the infrared modes only. The register bank main functions are listed in

Table 1. Descriptions of the various

registers are given in the following sections.

TABLE 1. Register Banks Summary

Bank

UART

Description

Mode

Global Control and Status Registers

Legacy Bank

Baud Generator Divisor and Extended Control

Identification and Shadow Registers

Timer and Counters

Infrared Control and Status FIFO

DS012549-4

FIGURE 4. Register Bank Architecture

PC87108AVHG Datasheet(PDF) 13 Page - National Semiconductor (TI)