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dc1748af

DEMO MANUAL DC1748A

OPERATING PRINCIPLES

The LTM2883 contains an isolated DC/DC conversion

system, including a boost converter and inverting charge

pump, with multiple LDO’s to deliver power to the three

output voltage rails from VCC. Isolation is maintained by

the separation of GND and GND2 where significant operat-

ing voltages and transients can exist without affecting the

operation of the LTM2883. The logic side ON pin enables

or shuts down the LTM2883. All logic side signals are

referenced to the logic supply pin VL. The LTM2883 is

available in two data bus configurations, SPI (-S) or I2C

(-I), and with two input voltage ranges, 3.0 to 3.6 volts

(-3) or 4.5 to 5.5 volts (-5).

SPI signaling is controlled by the logic inputs CS, SDI,

and SCK. SDOE controls the SDO output and is normally

connected to CS. The corresponding Isolated side output

signals are CS2, SDI2, and SCK2. SDO2 is the isolated

side SPI data input. All of the SPI communication channels

may be used as generic digital I/O.

I2C signaling is controlled by the logic inputs SDA and

SCL, corresponding to SDA2 and SCL2 on the isolated

side. The SCL channel is unidirectional supporting master

mode only I2C communication. SCL2 output is standard

CMOS push-pull drive. SDA signaling is bidirectional,

and includes an internal current source pull-up on SDA2

supporting up to 200pF of load capacitance.

Demo circuit 1748A is available in four configurations

supporting all versions of the LTM2883. Table 2 details

the demo circuit configurations.

Table 2.

DEMO CIRCUIT

INPUT VOLTAGE

COMMUNICATION

DC1748A-A

3.0V to 3.6V

SPI/Digital

DC1748A-B

4.5V to 5.5V

SPI/Digital

DC1748A-C

3.0V to 3.6V

I2C

DC1748A-D

4.5V to 5.5V

I2C

The demo circuit has been designed and optimized for low

RF emissions. To this end some features of the LTM2883

are not available for evaluation on the demo circuit. The

logic supply voltage VL is tied to VCC on the demo circuit,

and the ON pin is not available on the input pin header,

but may be controlled by jumper JP1. EMI mitigation

techniques used include the following.

1. Four layer PCB, allowing for isolated side to logic side

bridge capacitor. The bridge capacitor is formed be-

tween an inner layer of floating copper which overlaps

the logic side and isolated side ground planes. This

structure creates two series capacitors, each with

approximately .008" of insulation, supporting the full

dielectric withstand rating of 2500VRMS. The bridge

capacitor provides a low impedance return path for

injected currents due to parasitic capacitances of the

LTM2883’s signal and power isolating elements.

2. Discrete bridge capacitors (C3, C4) mounted between

GND2 and GND. The discrete capacitors provide ad-

ditional attenuation at frequencies below 400MHz.

Capacitors are safety rated type Y2, manufactured by

Murata, part number GA342QR7GF471KW01L.

3. Board/ground plane size has been minimized. This

reduces the dipole antenna formed between the logic

side and isolated side ground planes.

4. Top signal routing and ground floods have been opti-

mized to reduce signal loops, minimizing differential

mode radiation.

5. Common mode filtering is integrated into the input and

output pin headers. Filtering helps to reduce emissions

caused by conducted noise and minimizes the effects

of cabling to common mode emissions.

6. A combination of low ESL and high ESR decoupling is

used. A low ESL ceramic capacitor is located close to

the module minimizing high frequency noise conduction.

A high ESR tantalum capacitor is included to minimize

board resonances and prevent voltage spikes due to

hot plugging of the supply voltage.