Nexperia

74HCS32

Quad 2-input OR gate with Schmitt-trigger inputs

VM

VM

tW

tW

10 %

90 %

0 V

VI

VI

negative

pulse

positive

pulse

0 V

VM

VM

90 %

10 %

tf

tr

tr

tf

001aad983

DUT

VCC

VCC

VI

VO

RT

RL

S1

CL

open

G

Test data is given in Table 9.

Definitions for test circuit:

CL = load capacitance including jig and probe capacitance.

RL = load resistance.

RT = termination resistance should be equal to the output impedance Zo of the pulse generator.

S1 = test selection switch.

Fig. 11. Test circuit for measuring switching times

Table 9. Test data

Input

Load

S1 position

VI

tr, tf

CL

RL

tPHL, tPLH

tPZH, tPHZ

tPZL, tPLZ

VCC

2.5 ns

50 pF

1 kΩ

open

GND

VCC

74HCS32

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Product data sheet

Rev. 1 — 27 June 2025

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