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ICS841S01BGLF Datasheet(PDF) 1 Page - Integrated Device Technology

Part # ICS841S01BGLF
Description  PCI EXPRESS??CLOCK GENERATOR
PDF  16 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS841S01BGLF Datasheet(HTML) 1 Page - Integrated Device Technology

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PCI EXPRESS™ CLOCK GENERATOR
ICS841S01
IDT™ / ICS™ PCI EXPRESS CLOCK GENERATOR
1
ICS841S01BG REV. B MAY 23, 2007
PRELIMINARY
GENERAL DESCRIPTION
The ICS841S01 is a PLL-based clock generator
specifically designed for PCI_Express™Clock
Generation applications. This device generates a
100MHz HCSL clock. The device offers a HCSL
(Host Clock Signal Level) clock output from a clock
input reference of 25MHz. The input reference may be derived
from an external source or by the addition of a 25MHz crystal to
the on-chip crystal oscillator. An external reference may be applied
to the XTAL_IN pin with the XTAL_OUT pin left floating.
The device offers spread spectrum clock output for reduced EMI
applications. An I2C bus interface is used to enable or disable
spread spectrum operation as well as select either a down spread
value of -0.35% or -0.5%.
The ICS841S01 is available in both standard and lead-free
16-Lead TSSOP packages.
FEATURES
• One 0.7V current mode differential HCSL output pair
• Crystal oscillator interface, 25MHz
• Output frequency: 100MHz
• RMS period jitter: 3ps (maximum)
• Cycle-to-cyle jitter: 35ps (maximum)
• I2C support with readback capabilities up to 400kHz
• Spread Spectrum for electromagnetic interference (EMI)
reduction
• 3.3V operating supply mode
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS™
ICS
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
BLOCK DIAGRAM
PIN ASSIGNMENT
VSS_SRC
VDD_SRC
SRCT0
SRCC0
VDD_SRC
VSS_SRC
IREF
VSSA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD_SRC
SDATA
SCLK
XTAL_OUT
XTAL_IN
VDD_REF
VSS_REF
VDDA
ICS841S01
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
Divider
Network
PLL
OSC
I2C
Logic
SRCT0
SRCC0
Pullup
Pullup
XTAL_IN
XTAL_OUT
SDATA
SCLK
IREF
25MHz


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