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74LVC86A

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Product data sheet

Rev. 5 — 19 October 2011

6 of 15

Nexperia

74LVC86A

Quad 2-input EXCLUSIVE-OR gate

10. Dynamic characteristics

[1]

Typical values are measured at Tamb =25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.

[2]

tpd is the same as tPLH and tPHL.

[3]

Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

[4]

CPD is used to determine the dynamic power dissipation (PD in W).

PD =CPD  VCC2  fi  N+ (CL  VCC2  fo) where:

fi = input frequency in MHz; fo = output frequency in MHz

CL = output load capacitance in pF

VCC = supply voltage in Volts

N = number of inputs switching

(C

L  VCC

2

 f

o) = sum of the outputs

Table 7.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.

Symbol Parameter

Conditions

40 C to +85 C

40 C to +125 C Unit

Min

Typ[1]

Max

Min

Max

tpd

propagation delay

nA, nB to nY; see Figure 6

[2]

VCC = 1.2 V

-

11.0

-

-

-

ns

VCC = 1.65 V to 1.95 V

0.5

4.1

9.8

0.5

11.4

ns

VCC = 2.3 V to 2.7 V

1.0

2.4

5.6

1.0

6.5

ns

VCC = 2.7 V

1.0

2.5

5.8

1.0

7.0

ns

VCC = 3.0 V to 3.6 V

1.0

2.2

5.0

1.0

6.0

ns

tsk(o)

output skew time

VCC = 3.0 V to 3.6 V

[3]

-

-

1.0

-

1.5

ns

CPD

power dissipation

capacitance

per gate; VI =GND to VCC

[4]

VCC = 1.65 V to 1.95 V

-

12.5

-

-

-

pF

VCC = 2.3 V to 2.7 V

-

16.3

-

-

-

pF

VCC = 3.0 V to 3.6 V

-

19.7

-

-

-

pF