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NRF52810-QCAA-R7 Datasheet(PDF) 68 Page - Nordic Semiconductor |
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NRF52810-QCAA-R7 Datasheet(HTML) 68 Page - Nordic Semiconductor |
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68 / 483 page  Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field Value Id Value Description Enabled 1 Read: Enabled 5.3.9.2 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field Value Id Value Description A RW POFWARN Write '1' to Disable interrupt for POFWARN event See EVENTS_POFWARN Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled B RW SLEEPENTER Write '1' to Disable interrupt for SLEEPENTER event See EVENTS_SLEEPENTER Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled C RW SLEEPEXIT Write '1' to Disable interrupt for SLEEPEXIT event See EVENTS_SLEEPEXIT Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 5.3.9.3 RESETREAS Address offset: 0x400 Reset reason Unless cleared, the RESETREAS register will be cumulative. A field is cleared by writing '1' to it. If none of the reset sources are flagged, this indicates that the chip was reset from the on-chip reset generator, which will indicate a power-on-reset or a brownout reset. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field Value Id Value Description A RW RESETPIN Reset from pin-reset detected NotDetected 0 Not detected Detected 1 Detected B RW DOG Reset from watchdog detected NotDetected 0 Not detected Detected 1 Detected C RW SREQ Reset from soft reset detected NotDetected 0 Not detected 4430_161 v1.0 68 |
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