ST18-AU1 datasheet(38/87 Pages) STMICROELECTRONICS

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ST18-AU1

IPR: Interrupt priority register

(Address = 002A, Reset = 0000h, Read/Write)

The IPR register contains the priority level of each ITRQ0-7 interrupt input. IP0-7 priority level

is coded using two bits. The different values of IP are 0, 1, 2, 3 (0 lowest priority, 3 highest

priority).

When two ITRQ with the same priority level are requesting during the same cycle, the first

acknowledged interrupt is the one corresponding to the lowest number (for example, ITRQ0

acknowledged prior to ITRQ3).

ISPR: Interrupt stack pointer register

(Address = 002B, Reset = 0000h, Read/Write)

Note:

’-’ is RESERVED (read: 0, write: don’t care)

ISPR contains the number of stacked priority levels. If the ISPR value is directly written, the

SPLi/CPL values are modified. So the ICR register content is no longer significant but the

interrupt routine procedure is not affected. After reset, ISPR default value is 0

ISR: Interrupt status register

(Address = 002C, Reset = 0000h, Read/Write)

Note:

‘-’ is RESERVED (read: 0, write: don’t care)

876543

210

IP7(1:0)

IP6(1:0)

IP5(1:0)

IP4(1:0)

IP3(1:0)

IP2(1:0)

IP1(1:0)

IP0(1:0)

Bit

Function

Interrupt priority level (0, 1, 2 or 3) (default is 0)

876543

210

-----

--------

ISP(2:0)

Bit

Function

ISPR

Number of stacked priority levels (0, 1, 2 or 3)

9876

3210

IPE7 IPE6 IPE5 IPE4 IPE3 IPE2 IPE1 IPE0

Bit

Function

IPE

Interrupt pending bit

0: Reset when interrupt request is acknowledged (default)

1: Set when interrupt request is recorded

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