M2006-02A Datasheet Rev 1.0

2 of 8

Revised 28Jul2004

I n teg r at ed Circuit Systems , Inc. ● Netw o r ki ng & C o mmun ica t io ns ● ww w. icst.com ● te l (5 08 ) 8 5 2 - 54 00

Integrated

Circuit

Systems, Inc.

M2006-02A

Prod uct Data Sh eet

Figure 3: Detailed Block Diagram

Number

Name

I/O

Configuration

Description

1, 2, 3, 10, 14, 26

GND

Ground

Power supply ground connections.

4

9

OP_IN

nOP_IN

Input

External loop filter connections. See Figure 4.

5

8

nOP_OUT

OP_OUT

Output

6

7

nVC

VC

Input

11, 19, 33

VCC

Power

12, 13

FOUT1, nFOUT1

Output

No internal terminator

Clock output pairs. Differential LVPECL.

15, 16

FOUT0, nFOUT0

17

18

P1_SEL

P0_SEL

Input

P Divider controls. LVCMOS/LVTTL.

20

21

nDIF_REF1

Input

Reference clock input pair 1.

Differential LVPECL or LVDS.

DIF_REF1

22

REF_SEL

Input

Reference clock input selection. LVCMOS/LVTTL:

23

24

nDIF_REF0

Input

Reference clock input pair 0.

Differential LVPECL or LVDS.

DIF_REF0

25

NC

No internal connection.

27

28

FIN_SEL1

FIN_SEL0

Input

I

nput clock frequency selection. LVCMOS/LVTTL.

29

30

31

32

FEC_SEL0

FEC_SEL1

FEC_SEL2

FEC_SEL3

Input

FEC PLL divider ratio selection. LVCMOS/ LVTTL.

34, 35, 36

DNC

Do Not Connect.

Internal nodes. Connection to these pins can

cause erratic device operation.

Table 3: Pin Descriptions

Phase

Locked

Loop

(PLL)

M2006-02

SAW Delay Line

Phase

Shifter

VCSO

C

POST

C

POST

VC

nVC

R

POST

nOP_OUT

OP_OUT

R

POST

R

LOOP

R

LOOP

C

LOOP

C

LOOP

R

IN

R

IN

OP_IN

nOP_IN

Phase

Detector

Loop Filter

Amplifier

External

Loop Filter

Components

FOUT0

nFOUT0

FEC_SEL3:0

P0_SEL

FIN_SEL1:0

Rfec

Divider

MUX

0

REF_SEL

DIF_REF1

nDIF_REF1

DIF_REF0

nDIF_REF0

1

FOUT1

nFOUT1

P1_SEL

2

Mfec / Rfec

Divider LUT

4

Mfin Divider

LUT

Mfin Divider

Mfec Divider

P1 Divider

P = 1 ( P1_SEL = 0 )

or 4 ( P1_SEL = 1 )

P0 Divider

P = 1 ( P0_SEL = 0 )

or 4 ( P0_SEL = 1 )

A