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ST20-GP1 Datasheet(PDF) 104 Page - STMicroelectronics |
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ST20-GP1 Datasheet(HTML) 104 Page - STMicroelectronics |
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104 / 116 page  ST20-GP1 104/116 ® 19.2 Link timings Notes 1 This is the variation in the total delay through buffers, transmission lines, differential receiv- ers etc., caused by such things as short term variation in supply voltages and differences in delays for rising and falling edges. Table 19.2 Link timings Figure 19.2 Link timings Figure 19.3 Buffered Link timings Symbol Parameter Min Nom Max Units Notes tJQr LinkOut rise time 20 ns tJQf LinkOut fall time 10 ns tJDr LinkIn rise time 20 ns tJDf LinkIn fall time 20 ns tJQJD Buffered edge delay 0 ns ∆tJB Variation in tJQJD 20 Mbits/s 3 ns 1 10 Mbits/s 10 ns 1 5 Mbits/s 30 ns 1 CLIZ LinkIn capacitance @ f=1MHz 10 pF CLL LinkOut load capacitance 50 pF tJQf 90% 10% tJQr tJDf 90% 10% tJDr LinkOut LinkIn 1.5 V Latest tJQJD LinkOut LinkIn 1.5 V ∆tJB Earliest tJQJD |
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