ST72141K datasheet(62/132 Pages) STMICROELECTRONICS

62 / 132 page

ST72141K

62/132

MOTOR CONTROLLER (Cont’d)

8.1.4.4 Channel Manager

The channel manager consists of:

– A Phase State register with preload and polarity

function

– A multiplexer to direct the PWM to the odd and/

or even channel group

– A tristate buffer asynchronously driven by an

emergency input.

The block diagram is shown in Figure 39.

MPHST Phase State Register

A preload register enables software to asynchro-

nously update (during the previous commutation

interrupt routine for example) the channel configu-

ration for the next step: the OO[5:0] bits in the

MPHST register are copied to the Phase register

on a C event.

Table 24. Output State

Figure 39. Channel Manager Block Diagram

OP[5:0] bit

OO[5:0] bit

MCO[5:0] Pin

1 (OFF)

0-(PWM allowed)

0 (OFF)

1-(PWM allowed)

CFF bit

OO bits*

OE[5:0] bits

OS[2:0] bits*

Phasen Register*

SR bit

16-bit Timer PWM

Sampling frequency

DAC bit

Channel [5:0]

Current comparator

output

16-bit timer PWM

V0C1 bit

2.5-

µs

Filter

OP[5:0] bits

MOE bit

MPHST Register

MPOL Register

MCRB Register

MPAR Register

* = Preload register, changes taken into account at next C event.

MRCA Register

MCRA Register

Reg

DS,H

events:

Commutation

BEFMZero-crossing

End Of Demagnetization

Emergency Stop

Notes:

Updated/Shifted on R

Ratio Updated (+1 or -1)

Multiplier Overflow

R+/-

Current Mode

Voltage Mode

Regn

Updated with Regn+1 on C

Branch taken after C event

Branch taken after D event

ST72141K Datasheet(PDF) 62 Page - STMicroelectronics

ST72141K Datasheet(HTML) 62 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL