SDI

SCKR

IGNORED

VALID

IGNORED

t_biten

t_biten

tsdi_hold

tsdi_setup

D98AU971A

tsckr_min_high

BIT_EN

SCLK_POL=0

tsckr_min_low

tsckr_min_period

5.4.2. Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 0

tsdi_setup_min = 2ns

tsdi_hold_min = 3ns

tsckr_min_hi = 10ns

tsckr_min_low = 10ns

tsckr_min_lperiod = 50ns

t_biten (min) = 2ns

SRC_INT

D98AU972

5.4.3. SRC_INT

This is an asynchronous input used in ”broadcast’ mode.

SRC_INT is active low

t_src_low min duration is 50ns (1DSP clock period)

t_src_high min duration is 50ns (1DSP clock period)

XTI (INPUT)

XTO

CLK_OUT

D98AU973

5.4.4. XTI,XTO and CLK_OUT timings

txto = 1.40 + pad_timing (Cload_XTO) ns

tclk_out = 4 + pad_timing (Cload_CLK_OUT) ns

Note: In ”multimedia” mode, the CLK_OUT pad is DATA_REQ. In that case, no timing is given between th e XTI input and this pad.

SDI

SCKR

IGNORED

IGNORED

VALID

IGNORED

t_biten

t_biten

tsdi_hold

tsdi_setup

D99AU1038

tsckr_min_high

BIT_EN

SCLK_POL=4

tsckr_min_low

tsckr_min_period

5.4.2. Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 1

STA015-STA015B-STA015T

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