MIC5022BWM datasheet(7/10 Pages) MICREL

7 / 10 page

July 2005

MIC5022

Micrel, Inc.

Functional Description

Refer to the MIC5022 block diagram.

Input

A signal greater than 1.4V (nominal) applied to the MIC5022

INPUT

causes gate enhancement on an external MOSFET

connected to GATE H turning the high-side MOSFET on.

At the same time internal logic removes gate enhancement

from an external MOSFET connected to GATE L, turning the

low-side MOSFET off.

An internal pull-down resistor insures that an open INPUT

remains low, keeping the external high-side MOSFET turned

off and the low-side MOSFET turned on.

Enable (Active Low)

A signal greater than 1.4V (nominal) applied to the MIC5022

ENABLE

keeps both GATE outputs off. An internal pull-down

resistor insures that the MIC5022 is enabled if the pin is

open.

Gate Outputs

Rapid rise and fall times on the GATE output are possible

because each input state change triggers a one-shot which

activates a high-value current sink (10I2) for a short time.

This draws a high current though a current mirror circuit

causing the output transistors to quickly charge or discharge

the external FET’s gate.

A second current sink continuously draws the lower value

of current used to maintain the gate voltage for the selected

state.

Internal 15V Zener diodes protect the external high-side and

low-side MOSFETs by limiting the gate to source voltage.

Charge Pump (High-Side)

An internal charge pump utilizes an external “boost” capacitor

connected between VBOOST and the source of the external

FET (refer to TypicalApplication). The boost capacitor stores

charge when the FET is off. As the FET begins to turn on

the voltage on the source side of the capacitor increases

(because it is on the high side of the load) raising the VBOOST

pin voltage. The boost capacitor charge is directed through

the gate pin to quickly charge the FET’s gate to 15V maximum

above VDD. The internal charge pump maintains the gate

voltage by supplying a small current as needed.

Overcurrent Limiting (High or Low-Side)

Current source I1 charges CINT upon power up. An optional

externalcapacitorconnectedtoCTiskeptdischargedthrough

a FET Q1.

A fault condition (> 50mV from SENSE + to SENSE –) causes

the overcurrent comparator to enable current sink 2I1 which

overcomes current source I1 to discharge CINT in about 5µs

time. When CINT is discharged, the INPUT is disabled, the

FAULT

output is enabled, and CINT and CT are ready to be

charged. Since the INPUT is disabled the GATE output turns

off.

When the GATE output turns off the FET, the overcurrent

signal is removed from the sense inputs which deactivates

current sink 2I1. This allows CINT and the optional capacitor

connected to CT to recharge. A Schmitt trigger delays the

retry while the capacitor(s) recharge. Retry delay is increased

by connecting a capacitor connected to CT (optional).

The MIC5022’s low-side driver may be used without current

sensing by grounding both SENSE + and SENSE – pins. The

high-side driver may be used without current sensing by con-

necting SENSE + and SENSE – to the source of the external

high-side MOSFET.

Fault Output

The FAULT output is an open collector transistor. FAULT is

active at approximately the same time the output is disabled

by a fault condition (5µs after an overcurrent condition is

sensed). The FAULT output is open circuit (off) during each

successive retry (5µs).

VDD

Input

Fault

CTH

Enable

CTL

Gnd

VBOOST

Gate H

Sense H–

Sense H+

Gate L

Sense L–

Sense L+

10µF

0.01µF

+12V to +20V

MIC5022

VDD

Input

Fault

CTH

Enable

CTL

Gnd

VBOOST

Gate H

Sense H–

Sense H+

Gate L

Sense L–

Sense L+

10µF

MIC5022

0.01µF

TTL Input

(PWM signal)

TTL Input

(PWM signal)

Load

Figure 1. Basic Full-Bridge Circuit

Typical Full-Bridge Application

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