EMC646SP16J

4Mx16 CellularRAM

12

Preliminary

Burst Mode Operation

Burst mode operations enable high-speed synchronous READ and WRITE operations. Burst operations consist of a multi-clock

sequence that must be performed in an ordered fashion. After CE# goes LOW, the address to access is latched on the rising edge of the

next clock that ADV# is LOW. During this first clock rising edge, WE# indicates whether the operation is going to be a READ (WE# =

HIGH, Figure 6) or WRITE (WE# = LOW, Figure 7).

Figure 6: Burst Mode READ (4-word burst)

Note: Non-default BCR settings for burst mode READ (4-word burst): Fixed or variable latency; Latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay.

Diagram in the figure 6 is representative of variable latency with no refresh collision or fixed-latency access.

CLK

Latency Code 2 (3 clocks)

Don’t Care

Undefined

READ Burst Identified

(WE# = HIGH)

A[21:0]

ADV#

WE#

LB#/UB#

WAIT

DQ[15:0]

Address

Valid

D0

D1

D2

D3

CE#

OE#