EMC646SP16JS-55L datasheet(50/65 Pages) EMLSI

50 / 65 page

EMC646SP16J

4Mx16 CellularRAM

Preliminary

Figure 40. Burst WRITE at End-of-Row (Wrap Off)

Note:

1. Non-default BCR settings for burst WRITE at end of row: fixed or variable latency; WAIT active LOW; WAIT asserted during delay.

2. For burst WRITEs, CE# must go HIGH before the second CLK after the WAIT period begins(befor the second CLK after WAIT asserts with

BCR[8]=0, or before the third CLK after WAIT asserts with BCR[8]=1).

3. Devices from different CellularRAM vendors can assert WAIT so that the end-of-row data is input one cycle before WAIT asserts (DQ version A).

or the same cycle that asserts WAIT (DQ version B). This difference in behavior will not be noticed by controllers that monitor WAIT, or that use

WAIT to abort on an end-of-row condition.

CLK

ADV#

CE#

OE#

WAIT

DQ[15:0]

A[21:0]

tCLK

LB#/UB#

tHZ

End of Row

VIH

VIL

WE#

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

Valid

Intput

tKHTL

Valid

Intput

tHZ

Note 2

(A[6:0]=7Fh)

Don’t Care

High-Z

CE#

DQ[15:0]

End of Row

VIH

VIL

VIH

VIL

Valid

Intput

Valid

Intput

Note 2

Valid

Intput

tSP

tHD

tSP

tHD

(A[6:0]=7Fh)

Note 3

Version B

Version A

EMC646SP16JS-55L Datasheet(PDF) 50 Page - Emerging Memory & Logic Solutions Inc

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