85C51SND3B3 datasheet(21/263 Pages) ATMEL

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AT85C51SND3Bx

7632A–MP3–03/06

Idle Mode

Idle mode is a power reduction mode that reduces the power consumption. In this mode,

program execution halts. Idle mode freezes the clock to the CPU at known states while

the peripherals continue to be clocked (refer to Section “System Clock Generator”,

page 29). The CPU status before entering Idle mode is preserved, i.e., the program

counter and program status word register retain their data for the duration of Idle mode.

The contents of the SFRs and RAM are also retained.

Entering Idle Mode

To enter Idle mode, the user must set the IDL bit in PCON register while PMLCK is

cleared. The AT85C51SND3B enters Idle mode upon execution of the instruction that

sets IDL bit. The instruction that sets IDL bit is the last instruction executed.

Note:

If IDL bit and PD bit are set simultaneously, the AT85C51SND3B enter Power-down

mode. Then it does not go in Idle mode when exiting Power-down mode.

Exiting Idle Mode

There are 2 ways to exit Idle mode:

Generate an enabled interrupt.

–

Hardware clears IDL bit in PCON register which restores the clock to the CPU.

Execution resumes with the interrupt service routine. Upon completion of the

interrupt service routine, program execution resumes with the instruction

immediately following the instruction that activated Idle mode. The general-

purpose flags (GF1 and GF0 in PCON register) may be used to indicate

whether an interrupt occurred during normal operation or during Idle mode.

When Idle mode is exited by an interrupt, the interrupt service routine may

examine GF1 and GF0.

Generate a reset.

–

A logic high on the RST pin clears IDL bit in PCON register directly and

asynchronously. This restores the clock to the CPU. Program execution

momentarily resumes with the instruction immediately following the instruction

that activated the Idle mode and may continue for a number of clock cycles

before the internal reset algorithm takes control. Reset initializes the

AT85C51SND3B and vectors the CPU to address 0000h.

Note:

During the time that execution resumes, the internal RAM cannot be accessed; however,

it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port

pins, the instruction immediately following the instruction that activated Idle mode should

not write to a Port pin or to the external RAM.

Power-down Mode

The Power-down mode places the AT85C51SND3B in a very low power state. Power-

down mode stops the oscillator and freezes all clocks at known states (refer to the

Section “Oscillator”, page 27). The CPU status prior to entering Power-down mode is

preserved, i.e., the program counter, program status word register retain their data for

the duration of Power-down mode. In addition, the SFRs and RAM contents are

preserved.

Entering Power-down Mode

To enter Power-down mode, set PD bit in PCON register while PMLCK is cleared. The

AT85C51SND3B enters the Power-down mode upon execution of the instruction that

sets PD bit. The instruction that sets PD bit is the last instruction executed.

Exiting Power-down Mode

There are 2 ways to exit the Power-down mode:

Generate an enabled external interrupt.

–

The AT85C51SND3B provides capability to exit from Power-down using INT0,

INT1, and KIN3:0 inputs. In addition, using KIN input provides high or low level

exit capability (see Section “Keyboard Interface”, page 239).

Hardware clears PD bit in PCON register which starts the oscillator and restores

85C51SND3B3 Datasheet(PDF) 21 Page - ATMEL Corporation

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