AT89C52 datasheet(21/24 Pages) ATMEL

21 / 24 page

AT89C52

Shift Register Mode Timing Waveforms

AC Testing Input/Output Waveforms(1)

Note:

1. AC Inputs during testing are driven at V

CC - 0.5V

for a logic 1 and 0.45V for a logic 0. Timing measure-

ments are made at VIH min. for a logic 1 and VIL max.

for a logic 0.

Float Waveforms(1)

Note:

1. For timing purposes, a port pin is no longer floating

when a 100 mV change from load voltage occurs. A

port pin begins to float when a 100 mV change from

the loaded VOH/VOL level occurs.

Serial Port Timing: Shift Register Mode Test Conditions

The values in this table are valid for V

CC = 5.0V ± 20% and Load Capacitance = 80 pF.

Symbol

Parameter

12 MHz Osc

Variable Oscillator

Units

Min

Max

Min

Max

XLXL

Serial Port Clock Cycle Time

1.0

12t

CLCL

µs

QVXH

Output Data Setup to Clock Rising Edge

700

10t

CLCL-133

tXHQX

Output Data Hold After Clock Rising Edge

2tCLCL-117

XHDX

Input Data Hold After Clock Rising Edge

XHDV

Clock Rising Edge to Input Data Valid

700

10t

CLCL-133

XHDV

QVXH

XLXL

XHDX

XHQX

ALE

INPUT DATA

CLEAR RI

OUTPUT DATA

WRITE TO SBUF

INSTRUCTION

CLOCK

SET TI

SET RI

VALID

0.45V

TEST POINTS

- 0.5V

0.2 V

+ 0.9V

0.2 V

- 0.1V

LOAD

+ 0.1V

Timing Reference

Points

LOAD

- 0.1V

LOAD

+ 0.1V

- 0.1V

AT89C52 Datasheet(PDF) 21 Page - ATMEL Corporation

AT89C52 Datasheet(HTML) 21 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL