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ADE75 Datasheet(PDF) 25 Page - Analog Devices |
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ADE75 Datasheet(HTML) 25 Page - Analog Devices |
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25 / 148 page  Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 25 of 148 0 1 RX with wakeup disabled 1 1 RX with wakeup enabled Table 16. Power Management Interrupt Enable SFR (IPSME, 0xEC) Bit Location Bit Mnemonic Default Value Description 7 EPSR 0 Enables a PSM interrupt when the Power Supply Restored flag is set. 6 RESERVED 0 Reserved 5 ESAG 0 Enables a PSM interrupt when the voltage sag flag (FSAG) is set. 4 RESERVED 0 This bit must be kept cleared for proper operation 3 EVADC 0 Enables a PSM interrupt when the VDCIN ADC flag (FVADC) is set. 2 EBAT 0 Enables a PSM interrupt when the VBAT monitor flag (FBAT) is set. 1 EBSO 0 Enables a PSM interrupt when the Battery Switchover flag (FBSO) is set. 0 EVDCIN 0 Enables a PSM interrupt when the VDCIN monitor flag (FVDCIN) is set. Table 17. Scratch Pad 1 SFR (SCRATCH1, 0xFB) Bit Location Bit Mnemonic Default Value Description 7-0 SCRATCH1 0 Value can be written/read in this register. This value will be maintained in all the power saving modes of the ADE75xx/ADE71xx Table 18. Scratch Pad 2 SFR (SCRATCH2, 0xFC) Bit Location Bit Mnemonic Default Value Description 7-0 SCRATCH2 0 Value can be written/read in this register. This value will be maintained in all the power saving modes of the ADE75xx/ADE71xx Table 19. Scratch Pad 3 SFR (SCRATCH3, 0xFD) Bit Location Bit Mnemonic Default Value Description 7-0 SCRATCH3 0 Value can be written/read in this register. This value will be maintained in all the power saving modes of the ADE75xx/ADE71xx Table 20. Scratch Pad 4 SFR (SCRATCH4, 0xFE) Bit Location Bit Mnemonic Default Value Description 7-0 SCRATCH4 0 Value can be written/read in this register. This value will be maintained in all the power saving modes of the ADE75xx/ADE71xx Table 21. Key SFR (KYREG, 0xC1) Bit Location Bit Mnemonic Default Value Description 7-0 KYREG 0 Write 0xA7 to the KYREG SFR before writing the POWCON SFR, to unlock it Write 0xEA to the KYREG SFR before writing to the HTHSEC, SEC, MIN, or HOUR timekeeping register to unlock it.. Table 22. Power Control SFR (POWCON, 0xC5) Bit Location Bit Mnemonic Default Value Description 7 RESERVED X |
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