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STE2002 Datasheet(PDF) 42 Page - STMicroelectronics |
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STE2002 Datasheet(HTML) 42 Page - STMicroelectronics |
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42 / 51 page ![]() STE2002 42/51 Figure 50. Parallel interface Write timing Figure 51. Parallel interface Read timing ELECTRICAL CHARACTERISTICS (continued) AC OPERATION (VDD1 = 1.7 to 3.6V; VDD2 = 1.75 to 4.2V; Vss1,2 = 0V; VLCD = 4.5 to 11V; Tamb =-40 to 85°C; unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit PARALLEL INTERFACE TCY(EN) Enable Cycle Time VDD1 = 1.7V; Write; note 2, 6 150 ns TW(EN) Enable Pulse width 60 ns TSU(A) Address Set-up Time 30 ns TH(A) Address Hold Time 40 ns TSU(D) Data Set-Up Time 30 ns TH(D) Data Hold Time 30 ns TSU(D) Data Set-Up Time in read Mode 100 ns THU(D) Data Hold Time In Read mode 100 ns PD/C tSU(A) tSU(D) DB0-DB7 E tW(en) tHO(D) tCY(en) th(A) R/W WRITE PD/C tSU(A) tSUR(D) DB0-DB7 E tW(en) tHOR(D) tCY(en) th(A) R/W READ Don't Care |
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