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STE2002DIE2 Datasheet(PDF) 40 Page - STMicroelectronics |
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STE2002DIE2 Datasheet(HTML) 40 Page - STMicroelectronics |
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40 / 51 page ![]() STE2002 40/51 Figure 48. RESET timing diagram ELECTRICAL CHARACTERISTICS AC OPERATION (VDD1 = 1.7 to 3.6V; VDD2 = 1.75 to 4.2V; Vss1,2 = 0V; VLCD = 4.5 to 11V; Tamb =-40 to 85°C; unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit INTERNAL OSCILLATOR FOSC Internal Oscillator frequency VDD = 2.8V; Tamb = -20 to +70 °C 64 72 80 kHz FEXT External Oscillator frequency 20 100 kHz FFRAME Frame frequency fosc or fext = 72 kHz; note 1 75 Hz Tw(RES) RES LOW pulse width 5 µs Reset Pulse Rejection 1 µs TLOGIC (RES) Internal Logic Reset Time 5 µs TVDD VDD1 vs. VDD2 Delay 0 µs VDD1 RES INPUTS I/O (HOST) LR0118 VDD2 I/O (DRIVER) OSC OUT (DRIVER) OSCIN (HOST) INTERFACE OUTPUT Hi-Z BSY FLG RESET TABLE LOADED Tw(res) Hi-Z Tlogic(res) |
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