USBUF01P6

Technical information

5/9

2.1.2

ESD protection

In addition to the requirements of termination and EMC compatibility, computing devices are

required to be tested for ESD susceptibility. This test is described in the IEC 61000-4-2 and

is already in place in Europe. This test requires that a device tolerates ESD events and

remains operational without user intervention.

The USBUF01P6 is particularly optimized to perform ESD protection. ESD protection is

based on the use of device which clamps at:

This protection function is splitted in 2 stages. As shown in Figure 5. the ESD strikes are

clamped by the first stage S1 and then its remaining overvoltage is applied to the second

output.

Figure 5.

USBUF01P6 ESD clamping behavior.

Figure 6.

Measurement board.

To have a good approximation of the remaining voltages at both Vin and Vout stages, we

Vinput = 55.48 V

Voutput = 10.36 V

V

CL

V

BR

R

d

I

PP

⋅

+

=

ESD Surge

Vinput

Voutput

Rload

Rg

Rt

S1

Rd

V

BR

V

BR

V

PP

Device

to be

protected

USBUF01P6

Rd

S2

TEST BOARD

ESD

SURGE

15kV

Air

Discharge

Vin

Vout

Vinput

R

g

V

BR

R

d

V

g

⋅

+

⋅

R

g

-----------------------------------------------

=

Voutput

R

t

V

BR

R

d

Vinput

⋅

+

⋅

R

t

----------------------------------------------------------

=