M48T212V datasheet(12/35 Pages) STMICROELECTRONICS

12 / 35 page

Operation

M48T212V

12/35

Table 5.

Read mode AC characteristics

2.3

Write mode

The M48T212V is in the WRITE Mode whenever W (WRITE Enable) and E (Chip Enable)

are in a low state after the address inputs are stable. The start of a WRITE is referenced

from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising

edge of W or E. The addresses must be held valid throughout the cycle. E or W must return

high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable prior to the

initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of

WRITE and remain valid for tWHDX afterward.

G should be kept high during WRITE cycles to avoid bus contention; although, if the output

bus has been activated by a low on E and G a low on W will disable the outputs tWLQZ after

W falls.

When E is low during the WRITE, one of the on-board TIMEKEEPER® registers will be

selected and data will be written into the device. When EX is low (and E is high) an external

SRAM location is selected.

Note:

Care should be taken to avoid taking both E and EX low simultaneously to avoid bus

contention.

Symbol

Parameter(1)

Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 3.0 to 3.6V (except where noted).

M48T212V

Unit

–85

Min

Max

tAVAV

Read cycle time

tAVQV

Address valid to output valid

tELQV

Chip enable low to output valid

tGLQV

Output enable low to output valid

tELQX

(2)

CL = 5pF.

Chip enable low to output transition

tGLQX

(2)

Output enable low to output transition

tEHQZ

(2)

Chip enable high to output Hi-Z

tGHQZ

(2)

Output enable high to output Hi-Z

tAXQX

Address transition to output transition

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