M74HC165

Logic states

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3

Logic states

3.1

Truth table

Note:

a........h : the level of steady input voltage at inputs a through respectively QAn - QGn : the

level of QA - QG, respectively. Before the most recent transition of the clock.

3.2

Logic diagram

Figure 4.

Logic diagram

Note:

This logic diagram has not to be used to estimate propagation delays

Table 3.

Truth table

Inputs

Internal outputs

Outputs

Shift

/Load

Clock INH

Clock

SI

A..........H

QA

QB

QH

L

X

X

X

a..........h

a

b

h

HL

H

X

H

QAn

QGn

HL

L

X

L

QAn

QGn

HL

H

X

H

QAn

QGn

HL

L

X

L

QAn

QGn

H

X

H

X

X

No change

H

H

X

X

X

No change