ECP2 datasheet(29/386 Pages) LATTICE

29 / 386 page

2-26

Architecture

Lattice Semiconductor

LatticeECP2/M Family Data Sheet

MULTADDSUBSUM sysDSP Element

In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-

plier operation of operands A1 and B1. Additionally the operands A2 and B2 are multiplied and the result is added/

subtracted with the result of the multiplier operation of operands A3 and B3. The result of both addition/subtraction

are added in a summation block. The user can enable the input, output and pipeline registers. Figure 2-26 shows

the MULTADDSUBSUM sysDSP element.

Figure 2-26. MULTADDSUBSUM

Clock, Clock Enable and Reset Resources

Global Clock, Clock Enable and Reset signals from routing are available to every DSP block. Four Clock, Reset

and Clock Enable signals are selected for the sysDSP block. From four clock sources (CLK0, CLK1, CLK2, CLK3)

Multiplier

Add/Sub0

m+n

(default)

m+n

(default)

m+n+1

m+n+2

m+n+1

m+n

(default)

m+n

(default)

Multiplier

Add/Sub1

SUM

Multiplier B0

Multiplicand A0

Multiplier B1

Multiplicand A1

Multiplier B2

Multiplicand A2

Multiplier B3

Multiplicand A3

Signed A

Shift Register B In

Output

Addn0

Pipeline

CLK (CLK0,CLK1,CLK2,CLK3)

CE (CE0,CE1,CE2,CE3)

RST(RST0,RST1,RST2,RST3)

Input

Pipeline

Input

To Add/Sub0

To Add/Sub0, Add/Sub1

Pipeline

Signed B

Pipeline

Input

To Add/Sub0, Add/Sub1

Pipeline

Input

To Add/Sub1

Addn1

Pipeline

Shift Register A In

Shift Register B Out

Shift Register A Out

Input Data

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