PM6685 datasheet(47/52 Pages) STMICROELECTRONICS

47 / 52 page

PM6685

Design example

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10.5

Input capacitor

Maximum input capacitor RMS current is about 3.4A. Then ICinRMS > 3.4A

We put three 10uF ceramic capacitors with Irms = 1.5A.

10.6

Synchronous rectifier

OUT5: Schottky diode STPS1L30M

OUT3: Schottky diode STPS1L30M

10.7

Integrator loop

(Refer to Figure 30 on page 24)

OUT5: The ripple is greater than 30mV, then the virtual ESR network is not required.

CINT =1nF; Cfilt = 47pF; RINT = 1KΩ

OUT3: The ripple is greater than 30mV, then the virtual ESR network is not required.

CINT =1nF; Cfilt = 47pF; RINT = 1KΩ

10.8

Layout guidelines

The layout is very important in terms of efficiency, stability and noise of the system. It is

possible to refer to the PM6685 demoboard for a complete layout example.

For good PC board layout follows these guidelines:

●

Place on the top side all the power components (inductors, input and output capacitors,

MOSFETs and diodes). Refer them to a power ground plan, PGND. If possible, reserve

a layer to PGND plan. The PGND plan is the same for both the switching sections.

●

AC current paths layout is very critical (see Figure 41 on page 48). The first priority is to

minimize their length. Trace the LS MOSFET connection to PGND plan as short as

possible. Place the synchronous diode D near the LS MOSFET. Connect the LS

MOSFET drain to the switching node with a short trace.

●

Place input capacitors near HS MOSFET drain. It is recommended to use the same

input voltage plan for both the switching sections, in order to put together all input

capacitors.

●

Place all the sensitive analog signals (feedbacks, voltage reference, current sense

paths) on the bottom side of the board or in an inner layer. Isolate them from the power

top side with a signal ground layer, SGND. Connect the SGND and PGND plans only in

one point (a multiple vias connection is preferable to a 0 ohm resistor connection) near

the PGND device pin. Place the device on the top or on the bottom size and connect

the exposed pad and the SGND pins to the SGND plan (see Figure 41 on page 48).

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