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ST7LITE1XB Datasheet(PDF) 26 Page - STMicroelectronics |
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ST7LITE1XB Datasheet(HTML) 26 Page - STMicroelectronics |
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26 / 159 page  ST7LITE1xB 26/159 Figure 14. Clock Management Block Diagram CR6 CR9 CR2 CR3 CR4 CR5 CR8 CR7 RCCR fOSC MCCSR SMS MCO MCO fCPU fCPU TO CPU AND PERIPHERALS (1ms timebase @ 8 MHz fOSC) /32 DIVIDER fOSC fOSC/32 fOSC fLTIMER 1 0 LITE TIMER 2 COUNTER 8-BIT AT TIMER 2 12-BIT PLL 8MHz -> 32MHz fCPU CLKIN OSC2 CLKIN Tunable Oscillator 1% RC PLL 1MHz -> 8MHz PLL 1MHz -> 4MHz RC OSC ck_pllx4x8 /2 DIVIDER Option bits OSC,PLLOFF, CLKSEL[1:0] OSC 1-16 MHZ CLKIN CLKIN /OSC1 OSC /2 DIVIDER OSC/2 CLKIN/2 CLKIN/2 Option bits OSC,PLLOFF, CLKSEL[1:0] lock32 CR1 CR0 SICSR plldiv2 /2 PLLTST PLLDIV2 0 7 0 7 0 7 Note: The PLL cannot be used with the external resonator oscillator 1 |
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