ST72104GX-AUTO datasheet(83/135 Pages) STMICROELECTRONICS

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I2C BUS INTERFACE (Cont’d)

I2C CLOCK CONTROL REGISTER (CCR)

Read / Write

Reset Value: 0000 0000 (00h)

Bit 7 = FM/SM Fast/Standard I2C mode.

This bit is set and cleared by software. It is not

cleared when the interface is disabled (PE=0).

0: Standard I2C mode

1: Fast I2C mode

Bit 6:0 = CC[6:0] 7-bit clock divider.

These bits select the speed of the bus (fSCL) de-

pending on the I2C mode. They are not cleared

when the interface is disabled (PE=0).

Refer to the Electrical Characteristics section for

the table of values.

Note: The programmed fSCL assumes no load on

SCL and SDA lines.

I2C DATA REGISTER (DR)

Read / Write

Reset Value: 0000 0000 (00h)

Bit 7:0 = D[7:0] 8-bit Data Register.

These bits contain the byte to be received or trans-

mitted on the bus.

– Transmitter mode: Byte transmission start auto-

matically when the software writes in the DR reg-

ister.

– Receiver mode: the first data byte is received au-

tomatically in the DR register using the least sig-

nificant bit of the address.

Then, the following data bytes are received one

by one after reading the DR register.

I2C OWN ADDRESS REGISTER (OAR1)

Read / Write

Reset Value: 0000 0000 (00h)

7-bit Addressing Mode

Bit 7:1 = ADD[7:1] Interface address.

These bits define the I2C bus address of the inter-

face. They are not cleared when the interface is

disabled (PE=0).

Bit 0 = ADD0 Address direction bit.

This bit is don’t care, the interface acknowledges

either 0 or 1. It is not cleared when the interface is

disabled (PE=0).

Note: Address 01h is always ignored.

10-bit Addressing Mode

Bit 7:0 = ADD[7:0] Interface address.

These are the least significant bits of the I2C bus

address of the interface. They are not cleared

when the interface is disabled (PE=0).

I2C OWN ADDRESS REGISTER (OAR2)

Read / Write

Reset Value: 0100 0000 (40h)

Bit 7:6 = FR[1:0] Frequency bits.

These bits are set by software only when the inter-

face is disabled (PE=0). To configure the interface

to I2C specified delays select the value corre-

sponding to the microcontroller frequency fCPU.

Bit 5:3 = Reserved

Bit 2:1 = ADD[9:8] Interface address.

These are the most significant bits of the I2C bus

address of the interface (10-bit mode only). They

are not cleared when the interface is disabled

(PE=0).

Bit 0 = Reserved.

FM/SM CC6

CC5

CC4

CC3

CC2

CC1

CC0

ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0

FR1

FR0

ADD9 ADD8

fCPU

FR1

FR0

< 6 MHz

6 to 8 MHz

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