STE2007_06 datasheet(26/62 Pages) STMICROELECTRONICS

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Interface

STE2007

26/62

4.3.4

Driver TxData mode (Read mode)

If the R/W bit is set to logic 1 the chip will output data immediately after the slave address. If

the D/C bit during the last write access, is set to a logic 0, the byte read is the status byte.

Figure 18.

Communication protocol

LR0008d

MASTER ACK

COMMUNICATION

START

I2C START

COND

STE2007 ACK

R/W

SLAVE ADDRESS

SA1

Control Byte

COMMAND Byte

STE2007 ACK

Command Byte

D/C

000

SINGLE COMMAND

SEQUENCE

Control Byte

COMMAND Byte

STE2007 ACK

First Command Byte

D/C

000

MULTIPLE COMMAND

SEQUENCE

COMMAND Byte

STE2007 ACK

Last Command Byte

Control Byte

STE2007 ACK

D/C

000

SINGLE DATA

SEQUENCE

MULTIPLE DATA

SEQUENCE

DATA Byte

Data Byte

STE2007 ACK

Control Byte

DATA Byte

STE2007 ACK

First Data Byte

D/C

000

DATA Byte

STE2007 ACK

Last Data Byte

COMMUNICATION

STOP

I2C STOP

COND

STATUS BYTE READ

SEQUENCE

I2C START

COND

01111

0 A

STE2007 ACK

R/W

SLAVE ADDRESS

I2C START

COND

STATUS Byte

READ MODE

WRITE MODE

SA2

000

SA1 SA2

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