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STE2002DIE1 Datasheet(PDF) 48 Page - STMicroelectronics |
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STE2002DIE1 Datasheet(HTML) 48 Page - STMicroelectronics |
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48 / 61 page ![]() Electrical characteristics STE2002 48/61 TrDA Rise time of SDAH signal Cb=100pF(2) (3) (4) 10 ns TfDA Fall time of SDAH signal Cb=100pF (2) (3) (4) 10 80 ns TrDA Rise time of SDAH signal Cb=400pF(2) (3) (4) 20 ns TfDA Fall time of SDAH signal Cb=400pF(2) (3) (4) 20 160 ns TSU;STO Set-up time for STOP condition Cb=100pF(2) (3) 160 ns Cb Capacitive load for SDAH and SCLH 100 400 pF Cb Capacitive load for SDAH + SDA line and SCLH + SCL line 400 pF Parallel interface ( Figure 49, Figure 50) TCY(EN) Enable Cycle Time VDD1 = 1.7V; Write- (2) (5) 150 ns TW(EN) Enable Pulse width 60 ns TSU(A) Address Set-up Time 30 ns TH(A) Address Hold Time 40 ns TSU(D) Data Set-Up Time 30 ns TH(D) Data Hold Time 30 ns TSU(D) Data Set-Up Time in read Mode 100 ns THU(D) Data Hold Time In Read mode 100 ns Table 27. AC operation (continued) Symbol Parameter Test condition Min. Typ. Max. Unit |
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