| Electronic Components Datasheet Search |
|
STLS2F01 Datasheet(PDF) 40 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STLS2F01 Datasheet(HTML) 40 Page - STMicroelectronics |
|
40 / 48 page ![]() Electrical characteristics STLS2F01 40/48 Table 19. Input setup and hold time (Test Conditions: SYSCLK=100 MHz, PCICLK=66 MHz, CoreClk=1000 MHz) Parameter Min Tpy Max Unit PCI_* Signals Setup Time 3.0 ns PCI_* Signals Hold Time 0.0 ns LIO_* Signals Setup Time 3.0 ns LIO_* Signals Hold Time 0.0 ns Table 20. Output delay time (Test Conditions: SYSCLK=100 MHz, PCICLK=133 MHz, CoreClk=1000 MHz) Parameter Min Typ Max Unit PCI_* Signals Effective Delay 0.7 3.8 ns LIO_* Signals Effective Delay 1.5 6.0 ns DDDR2_A*/RAS*/CAS*/WE*/CS*/CKE*/ODT* Signals Effective Delay 1.5 ns DDR2_DQ*/DQM* Effective Delay 0.75 ns Table 21. JTAG parameters (Test Condition: TCK = 100 MHz) Parameter Min Typ Max Unit TCK high level time 2 5 8 ns TCK low level time 2 8 ns TCK rising time 1 1 ns TCK falling time 1 1 ns TRST pulse width 10 ns TDI,TMS setup time 3.5 4.4 ns TDI,TMS hold time 2.5 5.5 ns TDO output effective delay 1.28 ns TDO output disable delay 1.28 ns |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |