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STN8810 Datasheet(PDF) 7 Page - STMicroelectronics

Part # STN8810
Description  Mobile multimedia application processor
PDF  16 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STN8810 Datasheet(HTML) 7 Page - STMicroelectronics

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Overview
STn8810
6/15
1.4
ARM926EJ processor
The STn8810 CPU is an ARM926EJ reduced instruction set computer (RISC) processor.
This 32-bit processor core supports 32-bit ARM® and 16-bit Thumb instruction sets,
enabling the user to trade off between high performance and high code density.
The cached ARM CPU features a memory management unit (MMU) and is clocked at
264 MHz. It has a 32-Kbyte instruction cache and a 16-Kbyte data cache, and supports the
Jazelle™ extensions for Java acceleration.
It also includes an embedded trace module (ETM Medium+) for real-time CPU activity
tracing and debugging. It supports 4-bit and 8-bit normal trace mode and 4-bit demultiplexed
trace mode, with normal or half-rate clock.
1.5
Embedded memory units
●
32 Kbytes of public ROM (for boot purposes)
●
64 Kbytes of secured ROM (for security purposes)
●
40 Kbytes of public RAM
●
16 Kbytes of secured RAM (for security code and/or data)
●
1 Kbyte backup
1.6
Advanced security
The device contains 64 Kbytes of ROM and 16 Kbytes of RAM that are only accessible
when the system is in a trusted environment. An advanced security framework enables M-
commerce as well as authentication applications drawing on ST smartcard expertize:
●
SHA-1/DES/3DES hardware accelerators
●
True random number generator (RNG)
●
Secured watchdog timer
●
Unique die identification
1.7
Flexible static memory controller (FSMC)
The FSMC interfaces to off-chip multiplexed burst NOR Flash memory devices and NAND
Flash memory devices, and to CompactFlash/CF+ cards. The FSMC manages up to 3 chip-
selects of NOR Flash memories, and up to 2 chip-selects of NAND Flash memories or
CompactFlash/CF+ devices. The memory controller features error code correction
accelerated by hardware that reduces host CPU workload to support NAND Flash very fast
read/write transfers.
1.8
SDRAM memory controller (SDMC)
The SDMC is used to interface with single-data rate SDRAM (SDR-SDRAM) at 100 MHz
and double-data rate SDRAM (DDR-SDRAM) at 133 MHz. The SDMC manages up to two
chip-selects of 16-bit wide SDR-SDRAM or DDR-SDRAM. It can address up to 256 Mbytes
of SDRAM.



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