SN75DP118RHHT datasheet(7/15 Pages) TI

7 / 15 page

50%

tZ(HPD)

HPD_IN=VCC

LP =High

HPD_OUT=VDD

VCC

VDD

MAIN LINK PINS

ELECTRICAL CHARACTERISTICS

SWITCHING CHARACTERISTICS

SN75DP118

www.ti.com..................................................................................................................................... SLLS916A – SEPTEMBER 2008 – REVISED SEPTEMBER 2008

Figure 5. HPD Timing Diagram Number 3

The main link I/O of the SN75DP118 is designed to track the magnitude and frequency characteristics of the

input waveform and replicate them on the output. A feature has also been incorporated in the SN75DP118 to

either increase of decrease the output amplitude via the resistor connected between the DPadj pin and ground.

over recommended operating (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ΔVI/O(2)

VID = 200 mV, DPadj = 6.5 kΩ

ΔVI/O(3)

VID = 300 mV, DPadj = 6.5 kΩ

–24

Difference between input and output

voltages (VOD – VID)

ΔVI/O(4)

VID = 400 mV, DPadj = 6.5 kΩ

-45

-15

ΔVI/O(6)

VID = 600 mV, DPadj = 6.5 kΩ

-87

-47

-22

RINT

Input termination impedance

Ω

VIterm

Input termination voltage

over recommended operating (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tR/F(DP)

Output edge rate (20% - 80%)

Input edge rate = 80 ps (20% – 80%)

115

tPD

Propagation delay time

F = 1MHz, VID = 400 mV

200

240

280

tSK(1)

Intra-pair skew

F = 1MHz, VID = 400 mV

tSK(2)

Inter-pair skew

F = 1MHz, VID = 400 mV

tDPJIT(PP)

Peak-to-peak output residual jitter

dR = 2.7Gbps, VID = 400 mV, PRBS7

Submit Documentation Feedback

Product Folder Link(s): SN75DP118

SN75DP118RHHT Datasheet(PDF) 7 Page - Texas Instruments

SN75DP118RHHT Datasheet(HTML) 7 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Datasheet Download

Link URL