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STPCCONSUMER-II Datasheet(PDF) 1 Page - STMicroelectronics |
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STPCCONSUMER-II Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 93 page  STPC® CONSUMER-II X86 Core PC Compatible Information Appliance System-on-Chip Release 1.5 - January 29, 2002 1/93 Figure 0-1. Logic Diagram s POWERFUL x86 PROCESSOR s 64-BIT SDRAM UMA CONTROLLER s VGA & SVGA CRT CONTROLLER s 135 MHz RAMDAC s 2D GRAPHICS ENGINE s VIDEO INPUT PORT s VIDEO PIPELINE - UP-SCALER - VIDEO COLOUR SPACE CONVERTER - CHROMA & COLOUR KEY SUPPORT s TV OUTPUT - THREE-LINE FLICKER FILTER - ITU-R 601/656 SCAN CONVERTER - NTSC / PAL COMPOSITE, RGB, S-VIDEO s PCI MASTER / SLAVE / ARBITER s ISA MASTER / SLAVE s OPTIONAL 16-BIT LOCAL BUS INTERFACE s EIDE CONTROLLER s I²C INTERFACE s IPC - DMA CONTROLLER - INTERRUPT CONTROLLER - TIMER / COUNTERS s POWER MANAGEMENT UNIT s JTAG IEEE1149.1 DESCRIPTION The STPC Consumer-II integrates a standard 5th generation x86 core, a Synchronous DRAM controller, a graphics subsystem, a video pipeline, and support logic including PCI, ISA, and IDE controllers to provide a single consumer orientated PC compatible subsystem on a single device. The device is based on a tightly coupled Unified Memory Architecture (UMA), sharing memory between the CPU, the graphics and the video. The STPC Consumer-II is packaged in a 388 Plastic Ball Grid Array (PBGA). PBGA388 ST PC Co nsu me r II x86 Core Host I/F SDRAM CTRL SVGA GE VIP PCI m/s LB CTR PCI Bus ISA m/s IPC PCI m/s ISA Bus CRTC Cursor Monitor TV IDE I/F PMU Video Pipeline C Key K Key LUT Local Bus Encoder TVO JTAG |
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