Description

M34D64-W

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1

Description

devices organized as 8192 x 8 bits.

interface that uses a bidirectional databus and serial clock. The devices carry a built-in 4-bit

by the serial clock. Read and Write operations are initiated by a Start condition, generated

by the bus master. The Start condition is followed by a Device Select Code and Read/Write

bit (RW) (as described in Table 2.: Device select code), terminated by an acknowledge bit.

time, following the bus master’s 8-bit transmission. When data is read by the bus master, the

bus master acknowledges the receipt of the data byte in the same way. Data transfers are

terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.

Figure 1.

Logic diagram

Table 1.

Signal names

Signal name

Function

Direction

E0, E1, E2

Chip Enable

Input

SDA

Serial Data

I/O

SCL

Serial Clock

Input

WC

Write Control

Input

Supply voltage

Ground

AI02850c

3

E0-E2

SDA

VCC

M34D64-W

WC

SCL

VSS