33910 datasheet(21/44 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33910

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

INTERRUPT (IRQ)

The IRQ pin is a digital output used to signal events or

faults to the MCU while in Normal and Normal Request Mode

or to signal a wake-up from Stop Mode. This active low output

will transition to high, only after the interrupt is acknowledged

by a SPI read of the respective status bits.

WATCHDOG CONFIGURATION (WDCONF)

The WDCONF pin is the configuration pin for the internal

watchdog. A resistor can be connected to this pin to configure

the window watchdog period. When connected directly to

ground, the watchdog will be disabled. When this pin is left

open, the watchdog period is fixed to its lower precision

internal default value (150ms typical).

GROUND CONNECTION (AGND, PGND, LGND)

The AGND, PGND and LGND pins are the Analog and

Power ground pins.

The AGND pin is the ground reference of the voltage

regulator.

The PGND and LGND pins are used for high current load

return as in the LIN interface pin.

Note: PGND, AGND and LGND pins must be connected

together.

DIGITAL/ANALOG (L1)

The L1 pin is a multi purpose input. It can be used as a

digital input, which can be sampled by reading the SPI and

used for wake-up when 33910 is in Low Power Mode or used

as analog inputs for the analog multiplexer. When used to

sense voltage outside the module, a 33kohm series resistor

must be used on each input.

When used as a wake-up input L1 can be configured to

operate in Cyclic-Sense Mode. In this mode, one of the high

side switches is configured to be periodically turned on and

sample the wake-up input. If a state change is detected

between two cycles a wake-up is initiated. The 33910 can

also wake-up from Stop or Sleep by a simple state change on

L1.

When used as analog input, the voltage present on the L1

pins is scaled down by an selectable internal voltage divider

and can be routed to the ADOUT0 output through the analog

multiplexer.

Note: If L1 input is selected in the analog multiplexer, it will

be disabled as digital input and remains disabled in low

Power Mode. No wake-up feature is available in that

condition.

When the L1 input is not selected in the analog

multiplexer, the voltage divider is disconnected from that

input.

HIGH SIDE OUTPUTS (HS1 AND HS2)

These high side switches are able to drive loads such as

relays or lamps. Their structure is connected to the VS2

supply pin. The pins are short-circuit protected and also

protected against overheating.

HS1and HS2 are controlled by SPI and can respond to a

signal applied to the PWMIN input pin.

The HS1 and HS2 outputs can also be used during Low

Power Mode for the cyclic-sense of the wake input.

POWER SUPPLY (VS1 AND VS2)

Those are the battery level voltage supply pins. In an

application, VS1 and VS2 pins must be protected against

reverse battery connection and negative transient voltages,

with external components. These pins sustain standard

automotive voltage conditions such as load dump at 40V.

The high side switches (HS1 and HS2) are supplied by the

VS2 pin, all other internal blocks are supplied by VS1 pin.

VOLTAGE SENSE PIN (VSENSE)

This input can be connected directly to the battery line. It

is protected against battery reverse connection. The voltage

present in this input is scaled down by an internal voltage

divider, and can be routed to the ADOUT0 output pin and

used by the MCU to read the battery voltage.

The ESD structure on this pin allows for excursion up to

+40V and down to -27V, allowing this pin to be connected

directly to the battery line. It is strongly recommended to

connect a 10kohm resistor in series with this pin for protection

purposes.

HALL SENSOR SWITCHABLE SUPPLY PIN (HVDD)

This pin provides a switchable supply for external hall

sensors. While in Normal Mode, this current limited output

can be controlled through the SPI.

The HVDD pin needs to be connected to an external

capacitor to stabilize the regulated output voltage.

+5V MAIN REGULATOR OUTPUT (VDD)

An external capacitor has to be placed on the VDD pin to

stabilize the regulated output voltage. The VDD pin is

intended to supply a microcontroller. The pin is current limited

against shorts to GND and over-temperature protected.

During Stop Mode the voltage regulator does not operate

with its full drive capabilities and the output current is limited.

During Sleep Mode the regulator output is completely shut

down.

33910 Datasheet(PDF) 21 Page - Freescale Semiconductor, Inc

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