908E626 datasheet(21/44 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

908E626

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

RESET EXTERNAL SOURCE

External Reset Pin

The microcontroller has the capability of resetting the

SMARTMOS device by pulling down the RST pin.

Reset Mask Register (RMR)

TTEST—High Temperature Reset Test

This read/write bit is for test purposes only. It decreases

the overtemperature shutdown limit for final test. Reset clears

the HTRE bit.

• 1 = Low temperature threshold enabled.

• 0 = Low temperature threshold disabled.

HVRE—High Voltage Reset Enable Bit

This read/write bit enables resets on high voltage

conditions. Reset clears the HVRE bit.

• 1 = High voltage reset enabled.

• 0 = High voltage reset disabled.

HTRE—High Temperature Reset Enable Bit

This read/write bit enables resets on high temperature

conditions. Reset clears the HTRE bit.

• 1 = High temperature reset enabled.

• 0 = High temperature reset disabled.

SERIAL PERIPHERAL INTERFACE

The serial peripheral interface (SPI) creates the

communication link between the microcontroller and the

908E626.

The interface consists of four pins (see Figure 11):

• SS—Slave Select

•MOSI—Master-Out Slave-In

•MISO—Master-In Slave-Out

• SPSCK—Serial Clock (maximum frequency 4.0 MHz)

A complete data transfer via the SPI consists of 2 bytes.

The master sends address and data, slave system status,

and data of the selected address.

Figure 11. SPI Protocol

During the inactive phase of SS, the new data transfer is

prepared. The falling edge on the SS line indicates the start

of a new data transfer and puts MISO in the low-impedance

mode. The first valid data are moved to MISO with the rising

edge of SPSCK.

The MISO output changes data on a rising edge of

SPSCK. The MOSI input is sampled on a falling edge of

SPSCK. The data transfer is only valid if exactly 16 sample

clock edges are present in the active phase of SS.

Bit7

Bit0

Read

TTEST

HVRE

HTRE

Write

Reset

R/W

System Status Register

Read/Write, Address, Parity

Data (Register write)

Data (Register read)

Rising edge of SPSCK

Change MISO/MOSI

Output

Falling edge of SPSCK

Sample MISO/MOSI

Input

Slave latch

data

MOSI

MISO

SPSCK

908E626 Datasheet(PDF) 21 Page - Freescale Semiconductor, Inc

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