HD49340F/HF

Rev.1.0, Apr 20, 2004, page 13 of 22

Serial Interface Specifications

DI 00 (LSB)

Low

DI 01

Low

Low

High

Low

Low

Resister 2

Resister 0

Resister 4 to 7

Test Mode (can not be used)

Resister 3

Resister 1

Low

Low

High

High

Low

Low to High

Low to High

High

High

DI 02

DI 03

DI 04

DI 05

DI 06

DI 07

DI 08

DI 09

DI 10

DI 11

DI 12

DI 13

DI 14

DI 15 (MSB)

HGstop-Hsel [1]

HGain-Nsel [0]

SHA-fsel [0] (LSB)

SHA-fsel [1] (MSB)

SHSW-fsel [0] (LSB)

SHSW-fsel [1]

SHSW-fsel [2]

SHSW-fsel [3] (MSB)

Clamp-level [3]

Clamp-level [2]

Clamp-level [1]

Low: Normal operation mode

High: Sleep mode

SLP

Low: Normal operation mode

High: Standby mode

STBY

Low: CDSIN input mode

High: ADCIN input mode

CSEL

Clamp-level [0] (LSB)

C-Bias off

Clamp-level [4] (MSB)

Gray code [0] (TEST1)

Gray code [1]

Ave_4H

HGstop-Hsel [0]

PGA gain setting (LSB)

PGA gain setting

PGA gain setting

PGA gain setting

PGA gain setting

PGA gain setting

Output mode setting (LINV)

Output mode setting (MINV)

Output mode setting (TEST0)

PGA gain setting

PGA gain setting (MSB)

OBPinv, OBP inversion

Low_PWR

SPinv,

SPSIG/SPBLK/PBLK inversion

Low: Reset mode

High: Normal operation mode

RESET

HGain-Nsel [1]

SHSW

frequency

character-

istics

switching

SHAMP

frequency

character-

istics

switching

Table 10

Serial Data Function List

Cannot

be used.

All low

Cannot

be used.

All low

Cannot

be used.

All low

High-speed

lead-in

cancellation

time

High-speed

lead-in

gain

multiplication

Cannot

be used.

Cannot be used.

Timing Specifications

SCK

CS

SDATA

DI

00

DI

01

DI

02

DI

03

DI

04

DI

05

DI

06

DI

07

DI

08

DI

09

DI

10

DI

11

DI

12

DI

13

DI

14

DI

15

Latches SDATA

at SCK rising edge

Data is determined

at CS rising edge

Figure 8 Serial Interface Timing Specifications

50 ns

50 ns

50 ns



Min







5 MHz

Max

Gray_test [2]

0

Gray_test [0]

Gray_test [1]

0

0

1

1

0

Notes: 1.

2.

3.

4.

5.

6.

7.

8.

2 byte continuous communications.

SDATA is latched at SCK rising edge.

Insert 16 clocks of SCK while CS is low.

Data is invalid if data transmission is aborted during transmission.

The gain conversion table differs in the CDSIN input mode and the ADCIN input mode.

STBY: Reference voltage generator circuit is in the operating state.

SLP: All circuits are in the sleep state.

This bit is used for the IC testing, and cannot be used by the user.

The use of this address is prohibited.

Circuit current and the frequency characteristic are switched.

Data = 0: 36 MHz guarantee

Data = 1: 25 MHz guarantee