HD74LS669FPEL datasheet(6/9 Pages) RENESAS

Part #	HD74LS669FPEL

Description	Synchronous Up / Down 4-bit Binary Counter

PDF	9 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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6 / 9 page

HD74LS669

Rev.2.00, Feb.18.2005, page 6 of 8

Waveforms 1

Clock

Load

Data Inputs

A, B, C, D

Enable

Up/

Down

Enable

Input

Ripple

Carry

Output

1.3V

tTHL

tTLH

tPHL

tsu

tw (CK)

tPLH

VOH

VOL

10% 10%

90%

Notes:

tPLH and tPHL from enable T input to ripple carry output assume that the counter is at the

maximum count (QA through QD high).

Propagation delay time from up / douwn to ripple carry must be measured with the counter at

either aminimum or a maximum count. As the logic level of the up / down input is changed, the

riiple carry output will follow. If the count is minimum (0) are ripple carry output transition will

be in phase. If the count is macimum (15) the ripple carry output will be out of phase.

Input pulse; tTLH

≤ 15 ns, t

THL

≤ 6 ns, PRR = 1 MHz

HD74LS669FPEL Datasheet(PDF) 6 Page - Renesas Technology Corp