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M306V2EEFS Datasheet(PDF) 100 Page - Renesas Technology Corp |
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M306V2EEFS Datasheet(HTML) 100 Page - Renesas Technology Corp |
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100 / 271 page  Rev.1.40 Oct 06, 2004 page 100 of 269 M306V2ME-XXXFP, M306V2EEFP Figure 2.11.1 Block diagram of UARTi (i = 0 and 2) RxD0 1 / (n0+1) 1/2 UART 0 bit rate generator (address 03A116) Clock synchronous type (when internal clock is selected) UART reception Clock synchronous type UART transmission Clock synchronous type Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) Receive clock Transmit clock CLK0 Clock source selection CTS0 / RTS0 f1 f8 f32 Reception control circuit Transmission control circuit Internal External Vcc RTS0 CTS0 TxD0 Transmit/ receive unit (UART0) CLK polarity reversing circuit CTS/RTS disabled CTS/RTS disabled CTS/RTS selected n0 : Values set to UART0 bit rate generator (BRG0) n2 : Values set to UART2 bit rate generator (BRG2) RxD2 Reception control circuit Transmission control circuit 1 / (n2+1) 1/16 1/16 1/2 UART2 bit rate generator (address 037916) Clock synchronous type (when internal clock is selected) UART reception Clock synchronous type UART transmission Clock synchronous type Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) Receive clock Transmit clock CLK2 CTS2 / RTS2 f1 f8 f32 Vcc RTS2 CTS2 TxD2 (UART2) RxD polarity reversing circuit TxD polarity reversing circuit CTS/RTS disabled CTS/RTS disabled CTS/RTS selected CLK polarity reversing circuit Internal External Clock source selection Transmit/ receive unit 1/16 1/16 |
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