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M62343GP Datasheet(PDF) 3 Page - Renesas Technology Corp

Part # M62343GP
Description  8-Bit, 3-Channel D/A Converter (Buffered)
PDF  8 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M62343GP Datasheet(HTML) 3 Page - Renesas Technology Corp

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M62343GP
REJ03F0075-0300 Rev.3.00 Mar 25, 2008
Page 3 of 7
Absolute Maximum Ratings
Item
Symbol
Rated Value
Unit
Power supply voltage
VCC
–0.3 to 7.0
V
Input voltage
Vin
–0.3 to VCC+0.3 ≤ 7.0
V
Output voltage
VO
–0.3 to VCC+0.3 ≤ 7.0
V
Internal power consumption
Pd
200
mW
Operating ambient temperature
Topr
–20 to +85
°C
Storage temperature
Tstg
–40 to +125
°C
Electrical Characteristics
(Unless specified otherwise, VCC = +5 V ±10%, GND = 0 V, Ta = -20ºC to 85ºC)
Specification Values
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
Power supply voltage
VCC
2.7
5.0
5.5
V
0
0.8
2.7
At CLK = 1 MHz operation, IAO = 0 µA
D/A data: 6 Ah (at maximum current)
Power supply current
ICC
0
0.6
1.8
mA
DI = CLK = LD = GND, IAO = 0 µA
Input leakage current
IILK
–10
—
10
µA
VIN = 0 to VCC
Input voltage “L”
VIL
0
—
0.2Vcc
V
Input voltage “H”
VIH
0.5Vcc
—
Vcc
V
0.1
—
Vcc
−0.1
IAO = ±100 µA
Buffer amp output
voltage range
VAO
0.1
—
Vcc
−0.2
V
IAO = ±500 µA
Buffer amp output
drive range
IAO
–1.0
—
1.0
mA
Upper saturation voltage = 0.3 V
Lower saturation voltage = 0.2 V
Differential
nonlinearity error
SDL
–1.0
—
1.0
LSB
Nonlinearity error
SL
–1.5
—
1.5
LSB
Zero point error
SZERO
–2.0
2.0
LSB
Full-scale error
SFULL
–2.0
—
2.0
LSB
VCC = 5.12 V (20 mV/LSB)
No load (IAO = 0)
Oscillation limit output
capacitance
CO
—
—
0.1
µF
Buffer amp output
impedance
RO
—
5.0
—
Ω
AC Characteristics
(Unless specified otherwise, VCC = +5 V ±10%, GND = 0 V, Ta = -20ºC to 85ºC)
Specification Values
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
Clock “L” pulse width
tCKL
200
—
—
ns
Clock “H” pulse width
tCKH
200
—
—
ns
Clock rise time
tCR
—
—
200
ns
Clock fall time
tCF
—
—
200
ns
Data setup time
tDCH
30
—
—
ns
Data hold time
tCHD
60
—
—
ns
Load setup time
tCHL
200
—
—
ns
Load hold time
tLDC
100
—
—
ns
Load “H” pulse width
tLDH
100
—
—
ns
D-A output settling time
tLDD
—
—
300
µs
Until output reaches last 1/2 LSB



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