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HD151TS206SS Datasheet(PDF) 10 Page - Renesas Technology Corp |
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HD151TS206SS Datasheet(HTML) 10 Page - Renesas Technology Corp |
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10 / 34 page  HD151TS206SS Rev.1.00, Apr.28.2003, page 10 of 34 I 2C Controlled Register Bit Map (cont.) Byte8 Read Back Byte Count Register Bit Description Contents Type Default Note 7 Read back byte count Bit7 RW 0 6 Read back byte count Bit6 RW 0 5 Read back byte count Bit5 RW 0 4 Read back byte count Bit4 RW 1 3 Read back byte count Bit3 RW 1 2 Read back byte count Bit2 RW 1 1 Read back byte count Bit1 RW 1 0 Read back byte count Bit0 Writing to this register will configure byte Count and how many bytes will be read back. Default is 1Ehex = 30 bytes. RW 0 Byte9 Control Register Bit Description Contents Type Default Note 7 SSC2 Enable Bit B6[2] = 0 or B9[7] = 1 : SSC2 = OFF B6[2] = 1 & B9[7] = 0 : SSC2 = ON RW 0 6 SSC1 Enable Bit B6[2] = 0 or B9[6] = 1 : SSC1 = OFF B6[2] = 1 & B9[6] = 0 : SSC1 = ON RW 0 5 Clock Frequency Control Bit4 Latched input FS_4 at Power ON RW X 4 Clock Frequency Control Bit3 Latched input FS_3 at Power ON RW X 3 Clock Frequency Control Bit2 Latched input FS_2 at Power ON RW X 2 Clock Frequency Control Bit1 Latched input FS_1 at Power ON RW X 1 Clock Frequency Control Bit0 Latched input FS_0 at Power ON RW X See Table3 0 Frequency Select Mode Bit 0 = Freq. is selected by latched input FS(4:0) 1 = Freq. is selected by I 2C B9[5:1] RW 0 |
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