HD74ACT161/HD74ACT163

Rev.2.00, Jul.16.2004, page 3 of 8

Mode Select Table

SR

SR

SR

PE

PE

PE

PE

CET

CEP

Action on the Rising Clock Edge (

)

L

X

X

X

Reset (Clear)

H

L

X

X

Load (Pn

→ Qn)

H

H

H

H

Count (Increment)

H

H

L

X

No change (Hold)

H

H

X

L

No change (Hold)

Note:

1. For HD74ACT163

H :

High Voltage Level

L :

Low Voltage Level

X :

Immaterial

State Diagram

0

1234

5

6

7

8

9

10

11

12

13

14

15

Block Diagram

PE

CEP

CET

CP

MR ’161

’163

SR

CP

’163

ONRY

’161

ONRY

DETAIL A

DETAIL A

DETAIL A

DETAIL A

CP

CP

D

D

’161 ’163

TC

Please note that this diagram is provided only for the understanding of logic operations and should not be

used to estimate propagation delays.