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M64894GP Datasheet(PDF) 7 Page - Renesas Technology Corp

Part # M64894GP
Description  Serial Input PLL Frequency Synthesizer for TV/VCR
PDF  13 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M64894GP Datasheet(HTML) 7 Page - Renesas Technology Corp

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M64894FP/GP
Rev.2.00 Jun 14, 2006 page 7 of 12
Method of Setting Data
The input information to consist of 2 or data of 4 bytes to lead to chip address is received in I
2C bus receiver. It shows a
definition of bus protocol admitted in the following.
1_STA
CA
CB
BB
STO
2_STA
CA
D1
D2
STO
3_STA
CA
CB
BB
D1
D2
STO
4_STA
CA
D1
D2
CB
BB
STO
STA : Start condition
STO : Stop condition
CA : Chip address
CB : Control data byte
BB : Band SW data byte
D1
: Divider data byte
D2
: Divider data byte
The information of 5 bytes necessary for circuit operation is chip address and control data, band SW data of 2 bytes and
divider byte of 2 bytes. After the chip address input, 2 or data of 4 bytes are received.
Function bit is contained the first and the third data byte to distinguish between divider data and control data, band data,
and “0” goes ahead of divider data, and “1” goes ahead of control data, band SW data.
S
1-7
SCL
SDA
Address
CA
1-7
Data
Data
1-7
89
0ACK
STA
P
STO
89
ACK
89
ACK
Write Mode Format
Byte
MSB
LSB
Address byte
1
1
0
0
0
MA1
MA0
0
A
Divider byte 1
0
N14
N13
N12
N11
N10
N9
N8
A
Divider byte 2
N7
N6
N5
N4
N3
N2
N1
N0
A
Control byte1
1
CP
T2
T1
T0
RSa
RSb
OS
A
Band SW byte
X
X
X
X
BS4
BS3
BS2
BS1
A
Read Mode Format
Byte
MSB
LSB
Address byte
1
1
0
0
0
MA1
MA0
1
A
Status byte 1
POR
FL
X
X
X
A2
A1
A0
A



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