HD74HC259

Rev.2.00 Jan 31, 2006 page 2 of 9

Function Table

Inputs

Clear

G

Output of Addressed

Latch

Each Other Output

Function

H

L

D

Qio

Addressable latch

H

H

Qio

Qio

Memory

L

L

D

L

8-line demultiplexer

L

H

L

L

Clear

Select Inputs

C

B

A

Latch Addressed

L

L

L

0

L

L

H

1

L

H

L

2

L

H

H

3

H

L

L

4

H

L

H

5

H

H

L

6

H

H

H

7

Notes: 1. D: the level at the data input

2. Qio: the level of Qi (i = 0, 1, ···7, as appropriate) before the indicated steady-state input conditions were

established.

Pin Arrangement

(Top view)

1

2

3

4

5

6

7

8

A

B

C

GND

Clear

Enable

16

15

14

13

12

11

10

9

B

C

CLR

G

D

A

Data

input

Outputs

Outputs

Latch

select