H838799 datasheet(21/686 Pages) RENESAS

21 / 686 page

Rev. 1.00 Jul. 11, 2007 Page xxi of xxxviii

20.4

Operation ........................................................................................................................... 448

20.4.1 A/D Conversion .................................................................................................... 448

20.4.2 External Trigger Input Timing.............................................................................. 449

20.4.3 Operating States of A/D Converter ....................................................................... 449

20.5

Example of Use.................................................................................................................. 450

20.6

A/D Conversion Accuracy Definitions .............................................................................. 453

20.7

Usage Notes ....................................................................................................................... 455

20.7.1 Permissible Signal Source Impedance .................................................................. 455

20.7.2 Influences on Absolute Accuracy ......................................................................... 455

20.7.3 Other Usage Notes ................................................................................................ 456

Section 21 I

2C Bus Interface 2 (IIC2) ................................................................457

21.1

Features .............................................................................................................................. 457

21.2

Input/Output Pins ............................................................................................................... 459

21.3

Register Descriptions ......................................................................................................... 460

21.3.1 I

2C Bus Control Register 1 (ICCR1) ..................................................................... 460

21.3.2 I

2C Bus Control Register 2 (ICCR2) ..................................................................... 463

21.3.3 I

2C Bus Mode Register (ICMR)............................................................................ 465

21.3.4 I

2C Bus Interrupt Enable Register (ICIER) ........................................................... 467

21.3.5 I

2C Bus Status Register (ICSR)............................................................................. 469

21.3.6 Slave Address Register (SAR) .............................................................................. 472

21.3.7 I

2C Bus Transmit Data Register (ICDRT)............................................................. 472

21.3.8 I

2C Bus Receive Data Register (ICDRR).............................................................. 472

21.3.9 I

2C Bus Shift Register (ICDRS)............................................................................ 472

21.4

Operation ........................................................................................................................... 473

21.4.1 I

2C Bus Format...................................................................................................... 473

21.4.2 Master Transmit Operation ................................................................................... 474

21.4.3 Master Receive Operation..................................................................................... 476

21.4.4 Slave Transmit Operation ..................................................................................... 478

21.4.5 Slave Receive Operation....................................................................................... 481

21.4.6 Clock Synchronous Serial Format ........................................................................ 482

21.4.7 Noise Canceller..................................................................................................... 485

21.4.8 Example of Use..................................................................................................... 485

21.5

Interrupt Request................................................................................................................ 490

21.6

Bit Synchronous Circuit..................................................................................................... 491

21.7

Usage Notes ....................................................................................................................... 492

21.7.1 Note on Issuing Stop Condition and Start (Re-Transmit) Condition .................... 492

21.7.2 Note on Setting WAIT Bit in I

2C Bus Mode Register (ICMR)............................. 492

21.7.3 Restriction on Transfer Rate Setting in Multimaster Operation............................ 492

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